Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools

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CMOS Inverter Design, Analysis and Layout in SKY130

Design and Analysis of CMOS Inverter using the gpdk045 and Cadence virtuoso

CMOS inverter schematic and layout design and analysis utilizing the skywater 130 nm pdk and numerous open source tools such as Xschem, NGSPICE, MAGIC, Netgen, and so on.

This project models the DC and transient behavior of a CMOS inverter using neural networks and LSTM. It predicts Vout based on parameters like Vdd, Vin, Vtn, W/L ratios, and simulates transient response under capacitive loads. Key operations include: DC Analysis,Transient Analysis, Dataset Generation, Critical Voltage Calculation and Visualization.

Static behavior analysis of a CMOS inverter.

This repository offers a hands-on exploration of CMOS inverter design and analysis using TSMC180nm in LTspice. It covers MOSFET model analysis, CMOS inverter design principles, and includes detailed LTspice setups for parameter extraction, making it an informative guide for digital circuit enthusiasts.

CMOS circuit design and SPICE simulation study covering NMOS behavior, inverter VTC, noise margins, and robustness analysis.

A resource for a bachelor's degree course in VLSI Design, focusing on CMOS gate energy use and design with MicroWind and PSpice. It delves into inverter construction, complex logic with Euler paths, and delay analysis.

This repository contains the design and analysis of a CMOS inverter using Cadence Virtuoso with GPDK90 technology. The project includes schematic and layout design, pre-layout and post-layout simulations, delay calculations, RC parasitics extraction, and final GDSII file generation.

DVD project for transient timing analysis for CMOS inverter

CMOS inverter design and analysis using Cadence Virtuoso, including transient & DC simulations

Design and Analysis of Simple CMOS Inverter using Cadence Virtuoso and NGspice

Design and Analysis of a CMOS inverter using the sky130 pdk and open source tools

Analysis and design of cmos inverter in cadence virtuoso with GPDK 90 and ADE L simulation environment

This repository contains the design, simulation, and analysis of a CMOS Inverter using industry-standard tools like Cadence Virtuoso. The project focuses on understanding and optimizing the fundamental building block of digital circuits—the CMOS inverter.

This project contains an LTspice simulation of a CMOS inverter, including schematic, netlist, and waveform analysis. The design demonstrates the switching characteristics of a CMOS logic gate.

Comprehensive CMOS inverter characterization including VTC, noise margins, delay, rise/fall times, power analysis, and parameter sweeps using NGSpice

This project was created after my second year of study. It involves designing a CMOS inverter in 90nm technology using Cadence, along with DC analysis and layout.

Advanced digital CMOS laboratory reports, including inverter and logic gate layout, timing analysis, noise margins, and PVT and Monte Carlo simulations.

Metal-Oxide-Semiconductor (CMOS) technology forms the backbone of modern digital circuits due to its low power consumption and high noise immunity.

This project involves the design and analysis of a CMOS inverter circuit using Cadence Virtuoso. The focus is on creating the schematic, performing layout design, and conducting transient analysis to verify the functionality and performance of the inverter.

This week focused on CMOS device characterization and inverter behavior analysis using the Sky130 PDK. It covered topics like NMOS I–V characteristics, VTC analysis, switching threshold, and power supply & process variation robustness — forming the foundation for analog and digital CMOS design understanding.

CMOS Circuit Design and Analysis project using SPICE with the SKY130 PDK, where all NMOS and PMOS technology parameters were sourced from SKY130 to perform accurate NMOS I-V modeling, CMOS inverter VTC analysis, switching threshold extraction, noise margin evaluation and circuit level verification.

This repository documents my CMOS design workshop using NgSpice and SKY130. It covers NMOS Id–Vds characteristics, velocity saturation, CMOS inverter VTC, switching threshold, dynamic behavior, noise margin analysis, and power/device variation robustness. All circuits are verified in NgSpice for accurate transistor-level simulation and analysis.

CMOS inverter designed in Magic VLSI using SCMOS technology, extracted into a SPICE netlist, and simulated in ngspice. Includes layout, extraction files, and a simulation wrapper with transient analysis and waveform outputs

Assignments and Projects for EE671: VLSI Design (IIT Bombay). Contains SPICE simulations, Python analysis scripts, Sky130 PDK layouts, and LaTeX reports. Focus areas: CMOS inverter design, logic gates, sequential circuits, and final project implementation.

This repository showcases the analysis of CMOS inverters, including delay, power consumption, and performance metrics. It features SPICE simulations, waveforms, and insights into design optimization for robust digital circuits.

This project involves the design and analysis of a CMOS inverter employing GPDK90 90nm technology in Cadence Virtuoso. Both pre-layout and post-layout simulations, such as DC and Transient analyses, are included to analyze the effect of physical layout on circuit performance.