CMOS standard cell library (schematic and layout) using Electric VLSI and SPICE sim, Spring 18

This project was to design the (schematic and layout) and simulate CMOS (1.8V) standard cells using the Electric VLSI and LTSpice software.

A standard CMOS cell library for ECE 6710 at the University of Utah.

Approximate squarers, VHDL source, synthesis reports from standard cell library and 0.25 um CMOS process parameters

Custom standard logic gates and flip-flops cell designed in Cadence Virtuoso using GPDK090 CMOS technology library. Build, testbench and evaluation

Designed a custom 62nm CMOS standard cell library and synthesized a Matrix Vector Multiplier using it. Created schematics, layouts, and verified cells with DRC/LVS/PEX. Generated liberty files, performed Place & Route, and conducted STA for optimal clock timing using industry-standard EDA tools.

About This project was to design the (schematic and layout) and simulate CMOS (1.8V) standard cells using the Electric VLSI and LTSpice software. Stars

CMOS Standard Cell Library & 1-Bit Full Adder: A bottom-up digital design project using LTspice. Features transistor-level implementation of primitives (NAND/NOR/XOR) and hierarchical design of a 1-Bit Full Adder.

No description available

A comprehensive VLSI cell library featuring 8 standard cells (INV, NAND2/3, NOR2, XOR2, AOI22, OAI21/22). Designed in 65nm technology with a fixed 5.66μm cell height. Includes schematic design, optimized custom layouts, DRC/LVS verification, and HSPICE characterization with 45fF loading.

A standard cell library for few CMOS circuits

No description available

Focused on CMOS inverter design, standard cell layout, RTL to GDSII flows, and physical design of adders. Deliverables include schematic, layout, PEX, RTL, synthesis, and PnR files using Sky130 PDK, Magic, OpenLane. Final project: Complete standard cell library characterization with timing, power, and parasitics.