This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

CNN acceleration on virtex-7 FPGA with verilog HDL

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

FPGA Accelerator for CNN using Vivado HLS

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

A FPGA Based CNN accelerator, following Google's TPU V1.

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

FPGA

FPGA implementation of Cellular Neural Network (CNN)

FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。

hls code zynq 7020 pynq z2 CNN

【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码

OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.

Efficient FPGA-Based Accelerator for Convolutional Neural Networks

Implementing CNN code in CUDA and OpenCL to evaluate its performance on NVIDIA GPUs, AMD GPUs, and an FPGA platform.

To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface.

Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools

CNN-Accelerator based on FPGA developed by verilog HDL.

Zynq/FPGA实现CNN手写数字(0-9)识别

verilog CNN generator for FPGA

A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA

How to Accelerate an Image Upscaling CNN on FPGA Using HLS

implement convolution neural network on FPGA based on VHDL design