Compiler for Neural Network hardware accelerators

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Deep Learning Accelerator (Convolution Neural Networks)

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)

Fully opensource spiking neural network accelerator

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Computer vision container that includes Jupyter notebooks with built-in code hinting, Anaconda, CUDA 11.8, TensorRT inference accelerator for Tensor cores, CuPy (GPU drop in replacement for Numpy), PyTorch, PyTorch geometric for Graph Neural Networks, TF2, Tensorboard, and OpenCV for accelerated workloads on NVIDIA Tensor cores and GPUs.

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

Energy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.

Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)

Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)

Automatic generation of FPGA-based learning accelerators for the neural network family

Hardware accelerator for convolutional neural networks

hardware accelerator for deep convolutional neural networks

Efficient FPGA-Based Accelerator for Convolutional Neural Networks

This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.

Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)

My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, Cheng Du, China. For more informantion about me and my research, you can go to [my homepage](https://github.com/hisrg). One of my research interests is architecture design for deep learning and neuromorphic computing. This is an exciting field where fresh ideas come out every day, so I'm collecting works on related topics. Welcome to join us!

Official Implementation of "Accel-GNN: High-Performance GPU Accelerator Design for Graph Neural Networks"

The Open Source Hardware Accelerator for Efficient Neural Network Inference