This is a SAR ADC Controller verilog implementation

A digital controller for 8 Channel 10-bit SAR ADC

Digital control logic for an 8-bit SAR ADC with SPI output and oversampling, written in VHDL and designed for ASIC implementation (GF180MCU).

A bare-metal analog joystick controller implemented on the Infineon PSoC 4100S Plus, where a potentiometer acts as a directional input device. The system uses register-level configuration of the SAR ADC, TCPWM timer, and UART to periodically sample analog input, demonstrating interrupt-driven timing and low-level embedded system design.

Successive Approximation Register (SAR) ADC Controller of Problem 2 in attached document. Spring 18.

No description available

This project implements a fully synchronous, parameterized N-bit Successive Approximation Register (SAR) logic controller in Verilog. The SAR logic is the core digital control unit used inside a SAR Analog-to-Digital Converter (ADC), performing a binary-search-based conversion of an analog input to an N-bit digital value.

A comprehensive project featuring an SPI-based Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) digital controller, verified within a RISC-V System-on-Chip (SoC) environment and implemented using the Sky130 process node.