This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

The design process, a 4-bit SAR ADC and its different component was designed using Cadence Virtuoso software. This SAR ADC system consists of a bootstrapped sample-and-hold switch, a capacitive digital-to-analog converter (DAC), a dynamic comparator, and a SAR logic. Overall, the 4-bit SAR ADC designed and implemented in this project.

IL2239 Project Course (SAR ADC Design)

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This repo contains all the resourses for the final year project implementing a NS-SAR ADC and its application

The SAR ADC is becoming one of the most common and sought after ADC in industry due to their robustness, speed, and low Figure of Merit. In this report we have designed a SAR ADC for San Jose State University EE 288 Mixed Signal Analog Design as a final class project.

2022 Capstone project - Design of SAR ADC

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Graduation project by a team of Cairo university, the project is an energy efficient zoom capacitance to digital converter using SAR ADC as the coarse converter and time domain delta sigma as the fine converter

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Faculty project - 6 bit SAR ADC

This repository is about design and implementation of a time interleaved SAR ADC in Cadence Virtuoso. In this project all the blocks of the ADC is customised and implemented from transistor level itself and no ideal block is used from the libraries of virtuoso.

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Junior Design Project - enhance 10-bit SAR ADC on PIC24FJ64GA002 to 14-bit

Micro Elec project, small ECU part, ignition delay calculation with TDC & SAR ADC

Micro Elec project, small ECU part, ignition delay calculation with TDC & SAR ADC

coarse fine successive approximation register (SAR) analog-to-digital converter (ADC) - an undergraduate project

This is a landing site for various Projects on SAR ADC, CNN security framework, Power-Side Channel Detection Circuit.

Repository related to my Final Year Project at NIT Andhra Pradesh which includes designing a SAR ADC for biomedical applications

This project includes the summer internship report of designing of 16-Bit low power SAR ADC with 45nm CMOS and 32nm CNTFET technology file.

This project implements a fully synchronous, parameterized N-bit Successive Approximation Register (SAR) logic controller in Verilog. The SAR logic is the core digital control unit used inside a SAR Analog-to-Digital Converter (ADC), performing a binary-search-based conversion of an analog input to an N-bit digital value.

Discrete 8-bit SAR ADC (STM32 Bare-Metal) While modern microcontrollers come with high-speed integrated ADCs, I wanted to strip away the "black-box" abstraction and implement the Successive Approximation Register logic from the ground up. This project is a discrete implementation of an 8-bit ADC using an STM32F4 and a custom R-2R resistor ladder.

A comprehensive project featuring an SPI-based Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) digital controller, verified within a RISC-V System-on-Chip (SoC) environment and implemented using the Sky130 process node.