Arithmetic coding library with statistical models like PPM and Context mixing (demonstrating core principles of probabilistic inference, ensemble learning in AI)

A decently performing, single file C# arithmetic compressor/decompressor with a nice interface.

Embeddable dynamic bit sequence compressor using arithmetic coding

Advanced lossless text compressor using trigram probability models + arithmetic coding. CPU-only, no GPU needed. Perfect for non-repetitive prose, articles, and documentation.

an arithmetic compressor

Noise gate, Expander, Compressor, Limiter on HiFi 3 Arithmetic Engine

No description available

Text Compressor in C++ using Arithmetic coding

A hardware-efficient, 4-tap transposed FIR filter utilizing hybrid approximate 4:2 compressors. This project demonstrates a complete RTL-to-GDSII ASIC flow using the SkyWater 130nm PDK and OpenLane, achieving significant area and power reduction by strategically trading off arithmetic precision for hardware efficiency.

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No description available

Arithmetic Compressor project

Arithmetic coding compressor

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Testing of C# versions of rANS compressor, fpaq0 compressor, arithmetic compressor

Compressor and decompressor(Arithmetic coding)

File compressor using adaptive arithmetic apprach

File compressor implementing Huffman and Arithmetic encodings

No description available

Implementation of an Arithmetic Coding compressor in python

Small program to implement arithmetic compressor for chroma74 electronic sign label. Adapted from atc1441

arithmetic coding compressor using an LLM. Social commentary on the power/excesses of the LLM era. joke(?) project

A compressor based on arithmetic compression for bin files and texts in Russian and English. Project in CMC MSU.

Tiered text compressor inspired by Hitchhiker's Guide to the Galaxy. LLM tokenization + LZ dedup + adaptive arithmetic coding + neural model predictions.

This is a text compressor I made that uses an LSTM trained on Shakespeare to do Arithmetic Coding. Mostly just a side project to help learn information theory.

This project verifies a 4:2 compressor design implemented using two full adders in SystemVerilog. The verification checks correct sum and carry generation for all possible input combinations, ensuring accurate arithmetic operation and reliable performance of the digital circuit.

A 3:2 compressor is a digital logic circuit used in arithmetic operations, specifically in the design of multipliers. It takes three binary inputs and reduces them to two outputs, performing partial addition while minimizing carry propagation delay. Here’s how it works:

Designed and simulated ultra low-voltage, low-power CMOS 5:2 compressors in Cadence Virtuoso, based on Figure 13 from the referenced IEEE paper. Focused on optimizing power, delay, and area for efficient high-speed arithmetic circuits used in VLSI and DSP applications.