A high-performance rules engine for IFTTT-style automation in Rust with zero-overhead JSONLogic evaluation

A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 16 (fp16).

Skills for building AI agents, workflows, and embodied intelligence applications with the dora-rs dataflow framework

Dataflow analysis for Rust

The Brief Chip is a Simple Soc project written in Spinal HDL , include a 3 stages RISCV CPU and a CNN Accelerator with RS Dataflow as Peripheral

a repo of a multi-language dataflow implementation ,That uses YAML description files to define dataflow. In essence, it's a derivative of projects like Dora and Zenoh-Flow, primarily intended for educational purposes to a greater extent. However, I will strive to make practical use of it

No description available

Real-time object detection on Raspberry Pi 5 with Hailo-8 AI accelerator, WebRTC streaming, and dora-rs dataflow

dora-rs node to controll an inference dataflow

Simple implementation of a differential dataflow model in Rust as practice

CLI, HTTP API & Visual Editor for managing dora-rs dataflow environments