Game Boy -related schematics

These are schematics and testbench of a 4-to-1 MUX published in "F. Chen, C. Zhang, L. Wang, Q. Pan and C. P. Yue, "A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS," IEEE ESSCIRC, Lisbon, Portugal, 2023, pp. 373-376".

Schematic and testbench for a Double-Tail comparator published in "L. Wang et al., "A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique," in IEEE TCASI, vol. 70, no. 7, pp. 2637-2650, July 2023."

These are schematic and testbench of a TAS-TIS post-amplifier published in "A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS," 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2.

Schematics for stuff I like

EB-AN

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Created for toolchain: https://cloud.ibm.com/devops/toolchains/ec3f636e-04a1-451a-aac7-3a8736909856?env_id=ibm:yp:eu-gb