SystemVerilog implementation of RISC-V RV32I_Zmmul & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verification

A dual-core lockstep (DCLS) subsystem for the CVA6. Also supports dual-core asymmetric multi-processing (AMP) when lockstep in not needed.

This project is on a Dual core Lockstep Processor in RISC-V for functional safety .

Chain-based project tracking for Human+AI collaboration. MCP server for structured session management.

Fork from tools/server in MVZ443

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FUSA Dual-Core Lockstep ASIC design of oMSP430 in 65nm tech

Sentinel Sim Core is a correctness-first, deterministic simulation kernel designed for lockstep, replay, and rollback systems.

Contributing to Functional Safety (FuSa) enablement by implementing Dual-Core Lockstep on the Ibex RISC-V processor, including RTL development, lockstep comparator and divergence-detection logic, synchronization checks, and validation of functional/timing consistency, along with performing backend (PD) activities for RTL-to-GDS readiness.

Klaxon-R is a deterministic RV32 RISC-V real-time core with a safety-oriented architecture, combining TCM-first execution, MPU-based memory semantics, and a lockstep-ready design for fault detection and containment.