Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Chinese translation of the iCE40 FPGA and verilog tutorial: https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki

verilog uart tested on the lattice ice40 and simulated with cocotb, inspired by Obijuan / open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Hands-on FPGA architecture tutorial using open-source tools: Yosys (Parmys + ABC) and VTR (Verilog-to-Routing)

Working through tutorials on "Verilog, Formal Verification and Verilator" by ZipCPU using IceStick FPGA and IceStorm Open Source project