Found 22 repositories(showing 22)
riscv
RISC-V Opcodes
chipsalliance
The Scala parser to parse riscv/riscv-opcodes generate
SpriteOvO
Parse RISC-V opcodes to provide more detailed structured data
No description available
MatthewObi
A user-level C++17 header-only RISC-V emulator generator using riscv-opcodes.
Seo-sang
riscv-opcodes
5rfcdsw2
riscv-opcodes-master
Timmmm
Generated Rust code from riscv-opcodes
wangchaoqun789
No description available
rmccrary
No description available
AnaBSF
RISC-V Opcodes for the Unlimited Vector Extension
PACO-CPU
No description available
Eclipse-Laboratories-Inc
No description available
luckidea
No description available
openql-org
No description available
evancheng1006
No description available
PolyArch
No description available
bowwwang
No description available
masfiyan
Refactored RISC-V Opcodes: Maintainable opcode definitions with enhanced documentation and automated tools for integration and checks.
SebastianZanker
Tool disassembles a given RiscV binary and shows the opcodes, the involved registers and the specific instructions (immediate, load, save, ...)
pgovekar46
Developed RISCV custom MOD and POW instructions in MARSS-RISCV using C and assembly, targeting high-efficiency arithmetic. Extended the RISC-V GNU toolchain to support the new instructions by integrating custom opcode, funct3, funct7 fields, and their match/mask encodings into the assembler-disassembler pipelines.
darthtakt
Developed RISCV custom MOD and POW instructions in MARSS-RISCV using C and assembly, targeting high-efficiency arithmetic. Extended the RISC-V GNU toolchain to support the new instructions by integrating custom opcode, funct3, funct7 fields, and their match/mask encodings into the assembler-disassembler pipelines.
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