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Afiddle is a 'fiddle' for the Alogic mid-level hardware design language. It allows the user to enter Alogic code in a browser editor window and immediately see the Verilog that is produced by the Alogic compiler.
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^3.0.0^1.19.0^4.0.1^4.17.1^8.1.0^1.9.1^1.3.0^0.12.7^3.2.1^14.3.125
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