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X86 Opcode and Instruction Reference
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corrected opcode 0FB9 that is documented in newer Intel manuals as UD1 instruction
cb9ea9aView on GitHubadded TZCNT instruction (BMI1); the processor is indicated with "-1" because values of this element needs to reviewed
38cff3dView on GitHubadded LZCNT instruction (it has its own CPUID feature flag, it's not a part of BMI1); the processor is indicated with "-1" because values of this element needs to reviewed
456f9e1View on GitHubupdated AAM and AAD instruction definitions to comply with the latest Intel manual (reported by Kashio)
606688eView on GitHubfixed opcode 0xCE INTO instruction (it is invalid in 64-bit mode); reported by Kashio
af50cfbView on GitHubfixed PINSRQ and PEXTRQ entries (reported by Kashio)
d160fb3View on GitHubfixed incorrect operands of MOV DRn, r64 instruction
fe8d450View on GitHubfixed incorrect operands of PAND and PMADDWD MMX instructions (reported by Kashio)
e1307c3View on GitHubadded notes on the J addressing method and on SIMD FP instructions with integer operand codes to README
5508bd4View on GitHubMerge branch 'master' of https://github.com/Barebit/x86reference
4f3527bView on GitHubadded note to various instructions operating on FP operands that are indicated as integer ones (reported by Kashio)
48e324cView on GitHub