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A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
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removing warmup_insts from DDR3/DDR4 default config files
898e071View on GitHubcleaning test_ddr3.py and updating it to print the results better
68732e8View on GitHubfixing a bug that causes unnecessary delay between two ACT commands issued to different bank;
9658765View on GitHubFixed a bug which made FCFS Scheduler fail an assert in DDR3 and DDR4. Also made Scheduler.h more readable (#74)
791df71View on GitHub