Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
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add: footprints for fiducial marks with ring on top layer (6mil)
5e70505View on GitHubfixed: fixed paste expansion rule from fiducial marks. Old value for top paste expansion was 0mm, now it is -1mm, that means no paste on fiducial marks and no holes in stencils.
9fea65aView on GitHubedit: type of thermal interface is now "Standard (No BOM)" instead of "Net Tie". This removes a warning in DRC
6fa4512View on GitHubedit: reduced pad size for thermal interface, removed solder mask expansion from this pads
b7eae46View on GitHubadd: schematics and footprints for HPC connectors (carrier card and mezzanine card side)
6fd9b70View on GitHubadd: datasheets for hpc connectors (samtec) and molex connectors (lpc and hpc)
f081026View on GitHub