A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. Targeted at the Rhino Project (see URL).
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Minor changes to Arc and Actors, making types more compliant for conversion to Verilog.
9f6065bView on GitHubCreated a system test bench for testing a single arc on a FPGA. A dataset is randomly generated, passed through an arc and checked on output.
5ecb956View on GitHubDouble-checked Actor Class still works with changed Arc class. Still only works for one dataset being passed through (i.e. doesn't do streaming) - needs to be addressed.
8710c98View on GitHubSorted out Arc and Arc Testbench. Fairly messy, but it works. There is still a limitation due to the loop count variables not being reset when they're equal, but can be dodged by making the variable larger.
ff1a54fView on GitHubAdded DFT and Reorder base classes for flexible radix FFT implementation
27fe32aView on GitHubAdded new DFT Actor to HDFT directory, as well as blank test script
d4391c6View on GitHubCompleted Pipelined Mux class. Also created subdirectory for HDFT work.
33f3d1bView on GitHubCompleted Butterfly Operation block for FFT, as well as test script for simulation and conversion
ea6f256View on GitHubAdded the Platforms directory, Rhino sub-directory and updated the README
0cd380aView on GitHubActor and Arc working in simulation, as well as conversion to Verilog
0473fd0View on GitHubCurrently reworking Actor and Arc model - doesn't currently work, but almost there!
230bf1eView on GitHubAdded actor development script, as well as began work on Actor base class
b9c29eeView on GitHubFurther work on Arc base class. Works with variable input-output ratios and size factors, although minor bug when inputs than outputs
a23954aView on GitHub