The start of a 64-bit RISC-V, out-of-order, superscalar CPU core.
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Add the parameterizable Instruction Queue FIFO (#3)
47d2a58
Fix formatting and comments in README Directories section (#2)
6b4fa9a
Merge pull request #1 from Jacob-Dudik/setup
39f1da9
Create core sv package
204019b
Add sv module template
776610d
Add instr wiki link
6cb2da7
Update README and ISA doc
ab6929f
Move templates folder.
3598ed3
Add SystemVerilog module template.
e22da22
Initial file structure.
347a484
Initial commit
8758503