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PaletiKrishnasai/Computer-Architecture - GitHub Explorer | GitHub Explorer | Trending | Compare

Computer-Architecture

PaletiKrishnasai•PUBLIC

Hardware designs modelled with verilog

cachecomputer-architecturefloating-point-adderfloating-point-multiplicationhardware-designslogic-unit

MIT License

Created on Jan 9, 2021

Updated on Oct 11, 2024

Stars

6

Forks

3

Watchers

6

Open Issues

0

Repository Health Score

❤️

40/100

Poor

Overall repository health assessment

Score Breakdown

Activity

Inactive - no updates in 3+ months

0/30

0%

pipelined-risc

register-file

verilog

Community

6 stars, 3 forks

0/30

0%

Documentation

Has description, wiki, license

20/20

100%

Maintenance

0.0% issue ratio

20/20

100%

Health score is calculated based on activity, community engagement, documentation quality, and maintenance practices

Languages

Verilog

99.5%

C

0.5%

Dependencies

No package.json found

This might not be a Node.js project

Top Contributors

1

PaletiKrishnasai

PaletiKrishnasai

User

26

commits

Recent Commits

Add files via upload

Paleti Krishnasai•5 years ago

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Paleti Krishnasai•5 years ago

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Delete output.txt

Paleti Krishnasai•5 years ago

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Delete Mul.v

Paleti Krishnasai•5 years ago

9faf137View on GitHub

Delete Adder.v

Paleti Krishnasai•5 years ago

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Paleti Krishnasai•5 years ago

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Update README.md

Paleti Krishnasai•5 years ago

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Paleti Krishnasai•5 years ago

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Update RegisterFile.v

Paleti Krishnasai•5 years ago

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Paleti Krishnasai•5 years ago

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Paleti Krishnasai•5 years ago

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Update README.md

Paleti Krishnasai•5 years ago

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Add files via upload

Paleti Krishnasai•5 years ago

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Delete FPA_FPM_guide.pdf

Paleti Krishnasai•5 years ago

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Update README.md

Paleti Krishnasai•5 years ago

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