WeiChungWu/vim-SystemVerilog - GitHub Explorer | GitHub Explorer | Trending

Stars

52

Forks

20

Watchers

52

Open Issues

3

Repository Health Score

🧡

60/100

Fair

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Active development - updated this week

30/30

100%

Recent Commits

add missing keywords

WeiChungWu•5 years ago

83683eaView on GitHub

move snippets to another resposity

WeiChungWu•5 years ago

be9984fView on GitHub

add missing keywords

WeiChungWu•5 years ago

7ce7adbView on GitHub

add missing keywords

WeiChungWu•9 years ago

627e3c0View on GitHub

add missing keywords

WeiChungWu•9 years ago

6974629View on GitHub

fixed for compiler directives

WeiChungWu•10 years ago

27d89e8View on GitHub

add missing keywords

WeiChungWu•10 years ago

636e00fView on GitHub

Updated README file

WeiChungWu•11 years ago

db66103View on GitHub

add LICENSE file

WeiChungWu•11 years ago

29182afView on GitHub

add minor UVM support and fixed typo

WeiChungWu•11 years ago

ac83dbbView on GitHub

Merge pull request #1 from jeffwheeler/master

WeiChungWu•12 years ago

ac744cfView on GitHub

Fix README clone URL

Jeff Wheeler•12 years ago

e82cae6View on GitHub

add `uvm_*_utils_begin/`uvm_*utils_end indenting

WeiChungWu•12 years ago

970b84bView on GitHub

change randsequence in syntax and indent

WeiChungWu•12 years ago

da2d774View on GitHub

add README

WeiChungWu•12 years ago

93e1de8View on GitHub

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vim-SystemVerilog

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