Wishbone SATA Controller
Stars
25
Forks
3
Watchers
Open Issues
0
Overall repository health assessment
No package.json found
This might not be a Node.js project
User
20
commits
WIP: TX COMINIT appears to work (still no RX)
5925084
FIX: PHY now generates proper TX clock & frequency
b302a41
NEW: SIM w/ PHY resets TX, waits for RX response
c35d38a
WIP: IP builds in sim -- but w/o SATA model
0d335f7
WIP: Added ZipCPU hooks to the top level test bench.
8989429
WIP ... ongoing
fd24641
FIX: ZipDMA updates from formal verification work added
86fc0f8
WIP: Work continues on the Verilog test bench infrastructure
db126a8
Updated Copyrights
cb3897f
FIX: Missing item in rtl/README
6c06af1
NEW: Transport layer includes DMA support
c64c8ce
WIP: TB model + RX Scrambler enable control
91c65fc
WIP: Project state snapshot
a97d130
TB NEW: Word level encoding, decoding, alignment detection
9e95484
NEW: 8B/10B encoder and decoder for TB
59bac45