FYP project. A VerilogHDL based hardware accelerator.
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wrap up the project
3b6f4a7
bitwidth=8
b281346
topmodule
d266e9d
compilation error
4ece810
precise shifting
8c68069
full function implemented
8a79cc7
shifting
0ab9b8a
quantization
384c636
pipelining
2e37f3e
top module implemented
12e4863
to systemverilog
5e5ac78
all submodules implemented
610b18d
delete outdated files
3b0ceb4
second conv layer
526aef8
first maxpooling layer, ReLU function implemented in conv1
b72ba3c