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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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external HLT removed and handled internally on core from IDACK, DDACK or CPR_ACK.
fbb60f5View on GitHubdata bus: duplicated logic for data routing moved from darkbridge and darkcache to the core.
f4ec3e3View on GitHubtest fw fix: 1kHz timer instead of 1MHz (leds now blink again!)
8539befView on GitHubfix on rv32i for xilinx build, test of hw/fw for little-endian.
675cf8dView on GitHubfixes after tests: the RMW cycle on BRAM must be enabled when caches are used.
3bde42eView on GitHubnew darkmac coprocessor replaces the mac16x16 on the core!
568afb0View on GitHubMerge pull request #100 from MrJake222/fix/comments
b78478fView on GitHub338
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