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A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Fix: Roll-back v1.2.0 and remove almost flags threshold
9172f26View on GitHubNew: Merge #10 joeldushouyu/async_fifo feature bringing almost flags thresold setup
804806cView on GitHubChange: Update source code to correct lint messages from Icarus Verilog
350f643View on GitHub