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Vim plugin to work easier with Verilog & SystemVerilog
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Change: Correct regex sub command to match new py 3.14 warning
62af4cfView on GitHubChange: Remove spaces into a parenthesis of a signal during instance creation
ea94714View on GitHubFix: Use regx to better replace keyword 'reg' and avoid corruption
a8dd034View on GitHubFix: fix an issue when parsing the verilog source which led to a wrong
b507a1dView on GitHub