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Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.
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54
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Updated NEORV32 to v1.12.2.8 and used Quartus Prime Lite v20.1.1
a005ba3View on GitHubHW breakpoints was disabled by setting CPU_EXTENSION_RISCV_Sdtrig to false. This was needed because debugging does not worked correct.
2a89198View on GitHubAdded link to the SEGGER Embedded Studio fpr RISC-V tutorial.
24502e9View on GitHubNEORV32 submodule removed because it will not downloaded in case of "Code > Download ZIP".
c4c91daView on GitHub