Vim syntax etc for Verilog and SystemVerilog
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cloning helper ctag functions from https://raw.githubusercontent.com/vhda/verilog_systemverilog.vim
c05c484View on GitHubFixed indent for Virtual & Static class/functions based on https://github.com/nickjones/verilog_systemverilog.vim/commit/10348c08aa8d0c4f788903a29f5a8c37b199e0f5
45e0f03View on GitHubChanged names from verilog_systemverilog to systemverilog
56d34f8View on GitHubMerge branch 'master' of http://github.com/morganp/vim-SystemVerilog
214bd61View on GitHub