new README

new README

Made a new temp reaREADME

Added another encoder pic

Added images for encoder and a new adc_top image

Renamed decoders to encoders

updated comp_block

added functionality and potential comparator with input CM range issues

Ethan's encoder design fully implemented. Just use shift+t to uncomment it in the adc_top

Adding the new files for the manual sky encoder

put buffer at end of 5t-ota for railing output

Added Flip's Macromodel for the comparator

added flip's macromodel

Started implementing the comp block. To start just use a open loop op amp with high gain to show peformance

verilog-a dac and encoder working