Quick-start document with example usage

Merge pull request #6 from ldoolitt/master

Squelch trailing whitespace

Put in some simple clock-domain crossings

Add cdc_snitch support

uart.v: rename bit to bit1, to avoid confusing SV-compatible parsers (like Verilator)

Churn in Makefiles

fpga/hdl/packet_rx.v: pipeline comparisons

Add tests in fpga/hdl

fpga/hdl: remove some simple Verilog lint

fpga/xilinx/chip.ucf: separate clock groups

fpga/firmware/cmd.c: remove C lint

fpga/firmware/io.c: remove C lint

add Ethernet-based control, status, and frequency setting

add 4-bit quantizer modes