fixed VGS > VDD in bootstrap circuit

final gds with nwell distance increased in bootstrap circuit

updated submodule

reverted back to normal n-wells

lvs check and HV nwell layer experiment

Update info.md

updated documentation

connected unused digital output pin to ground

final gds file

added submodule

removed submodule

fixed DCR errors in bootstrap cell

fixed DRC errors in latched_comparator

attempt to fix some DRC errors

fixed DRC errors in the offset_calibration cell