Updated project to Vivado 2018.2

Added project for CmodA7 board. Tested ok

Prettified indentation

Updated Freemind map

Added Trivial UART and very rudimentary integration (not even using decoder/mux) with test program in C. Run at 3144654 baud

Fixed C Blinky

Added Blinky application in C

Increased memory size to 1024 bytes

Fixed Keil blinky projects. Added bitstream generation for FPGA serial flash

Added source code and project file for BlinkySEV application

Fixed application path. Re-routed HREADY

Fixed warning in T-FF implementation

Added Keil project for debugging

Substituted AHB ROM with preinitialized AHB RAM

Updated Freemind diagram