A project on UVM to verify the functionality of LCD controller design. A UVM testbench was created from scratch. AHB master/slave agents created to get the data in memory for LCD controller to access the data. Monitors and scoreboards were created to compare the data from LCDVD output to expected output in a file. Also wrote a logic to compare the number of cycles between two frame pulses with the expected number of cycles in a file. This was done such that the frame is received in the two frame pulses.