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Development of a processor, in Verilog, able to executes Python algorithm.
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17
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Updated the binary code file and the mux map. The RTL image was also updated.
32abfddView on GitHubUpdated the ULA map and binary code list. Added new supported instructions.
91764ceView on GitHubCreated the control unit file with inputs and outputs only. Still waiting for the state machine.
4daaf61View on GitHubFixed warnings (except the memory inicialization warning because it's wasn't defined a method for that).
3497149View on GitHubAdded hardware specifications with ula and muxes maps and other informations.
f8f7ca9View on GitHub