clean up Clarvi

add tolerance for variable latency

fix bug on wait request on cycle after read request

No need to test if the build directory already exists

Remove binary files

Add an ECALL handler to catch the end of program in hardware

Add 0x to all hex prinouts, print register being written to dscratch

Build simulation wrapper when simulating

Fix instret

Corrected documentation in clarvi, added missing file

Added clarvi Qsys component

Initial commit