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Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Merge pull request #3467 from verilog-to-routing/feature-ap-large-tile-leg
59ac66bView on GitHubMerge pull request #3468 from verilog-to-routing/arch_rr_graph_warn_msg
8f9ceabView on GitHubMerge remote-tracking branch 'origin/master' into feature-ap-large-tile-leg
ebd3594View on GitHubUpdated documentation to use tile instead of sub-tile
b3ed4f4View on GitHubMerge pull request #3466 from verilog-to-routing/fp_regex_attribute
a3150f8View on GitHub[cli] rename warn_arch_rr_lookahead to device_model_warnings
6b0fbb1View on GitHub[libs][libarch] pass warn_arch_rr_lookahead to arch_check
584479dView on GitHubMerge pull request #3469 from verilog-to-routing/dependabot/submodules/libs/EXTERNAL/yaml-cpp-1870e4b
a5b3a37View on GitHubBump libs/EXTERNAL/yaml-cpp from `05c050c` to `1870e4b`
1047835View on GitHub