Verilog/SystemVerilog Syntax and Omni-completion
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Merge pull request #233 from vhda/indent/eos_increment_decrement
74e533bView on GitHubIndent: Improve end-of-statement regexp to ignore increment/decrement
e42291aView on GitHubMerge pull request #210 from vhda/indent/indent_assign_on_symbol
5bf3601View on GitHubMerge pull request #220 from vhda/verilog_disable_indent_lst_fix
0141e62View on GitHubFunc: Only set g:verilog_disable_indent_lst if not already existing
664d3adView on GitHubMerge pull request #206 from vhda/indent/standalone_blocks
9fb7fefView on GitHubTest: Validate indentation with standalone blocks enabled
a36b688View on GitHubIndent: Allow indentation aligned with block start keyword
242f7adView on GitHub