Back to search
Top Contributors
11
commits
Indent & syntax script for Verilog and SystemVerilog
Stars
1
Forks
1
Watchers
1
Open Issues
0
Overall repository health assessment
No package.json found
This might not be a Node.js project
11
commits
Version 1.0: Fixed incorrect highlighting of numbers and times.
b4c7fa3View on GitHubVersion 0.7: Fixed issue with assert and cover property statements causing indent.
e5dec4dView on GitHubVersion 0.4: oops, forgot to uncomment finish lines in load checks
c41149eView on GitHub