Found 138 repositories(showing 30)
raulbehl
100 Days of RTL
ekb0412
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
snbk001
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
hughbyrne10
100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves committing to working on RTL based digital designs for 100 consecutive days. The goal is to build a solid foundation of knowledge and experience in the field.
ShashankSirohiya
I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
Artityagi123456789
No description available
Vidhi24-hub
No description available
Nidhinchandran47
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
kartiksamtani
This is a passion project where I aim to explore the RTL design topics of my interest.
merledu
100 Days of CHISEL inspired by 100DaysOfRTL
kalai-rajan
Collection of basic RTL Design and Verification Codes.
adithyamallisetti
No description available
Kethasriramya2912
"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"
GOURAV-CTRL
No description available
SSHHRREEY
No description available
abdelazeem201
Every Day I will be uploading an RTL code with Synthesized Design and TB for RISC CPU Design
Ahsan-Toufiq
System-Verilog
varunmadhavam
#100daysofrtl
Navya23Toluchuri
No description available
aasthadave9
100 Days of RTL
SailajaPeddakotla
This is the progress of 100 days of RTL and codes will be shared
Kanishk-K-U
No description available
Divya-i
Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.
Marcotronics
Inspired by the #100daysofrtl challenge and @raulbehl to learn SystemVerilog by coding a module every day and improve my design and verification skills.
SougataDe1
No description available
GeetikaTP
The Verilog Codes for various circuits are implemented in Quartus Prime.
RadhaDharani
No description available
muhammadtalhasami
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
tarungampala
100DAYSOFRTL PROJECTS
adityaB02
RTL (Register Transfer Level) design/digital logic design in system verilog(.sv) and use of verification methodologies.