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"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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180
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Merge branch 'main' of https://github.com/ekb0412/100DaysofRTL
bac87e4View on GitHubMerge branch 'main' of https://github.com/ekb0412/100DaysofRTL
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