16-bit Adder Multiplier hardware on Digilent Basys 3

Verilog Implementation of 32-bit Floating Point Adder

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions, Control circuits like State Machines, and DSP applications like FFT.

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining

Floating Point Adder in VHDL and Verification of result with matlab code

FP16 Half precision floating point (IEEE754 2008) adder + multiplier

explore different implementations of adders and study their characteristics.

Hardware designs modelled with verilog

No description available

Computer Architecture Projects

Floating Point Adder and Multiplier

Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.

Design, functional simulation, and implementation (synthesis, placement and routing) of a Floating Point Adder in Verilog using the Xilinx Vivado® toolset. I also, test the design on Zedboard under different configurations.

IEEE 754 Standard based Verilog coded Floating Point Adder

EE278 project

No description available

This is the VHDL code for a floating point adder

5-stage pipelined IEEE single-precision (SP) floating-point (FP) adder, The design has two parts: Part A Designed an un-pipelined SP FP adder, with results in the form of value and waveforms for certain test cases. Part B Modified the design to the 5-stage pipelined FP adder. This design takes 12 cycles to output all 8 cases. Stage 1: Compares the exponents and determine the amount of shifts required to align the mantissa to make the exponents equal (alignment-1). Stage 2: Right-shift the mantissa of the smaller exponent by the required amount (alignment-2). Stage 3: Compares the two aligned mantissas and determine which is the smaller of the two. This is followed by takeing 2’s complement of the smaller mantissa if the signs of the two numbers are different (addition). Stage 4: Add the two mantissas. Then, determine the amount of shifts required and the corresponding direction to normalize the result (normalization-1). Stage 5: Shift the mantissa to the required direction by the required amount. Adjust the exponent accordingly and check for any exceptional condition (normalization-2).

VHDL implementation of multiplier and adder/substracter for IEEE floating point standard

IEEE-754 Compliant Floating Point Unit (FPU)

A Transformer(gemma3N E4B LLM)accelerator based on a 2D (Floating-Point) Systolic Array, bitShift-only-Adder, architecture and dynamic multi channel memory management optimization techniques designed by SystemVerilog for edge devices. Target board: KV260(FPGA), Tool: Xilinx Vivado

Contains the project resources of the course CSE306. These were group projects.

Contains codes and designs of computer architecture assignments

Designed, using Verilog, a single cycle and a 2-stage pipelined version of a Floating Point Adder according to the IEEE-754 format. This project is designed to target a Xilinx Zedboard. To test our implementation on the actual hardware, we used detachable 7-segment displays.

No description available

floating point adder

In this project a 32 bit Floating point adder was designed using Verilog HDL. This design was pipelined to reduce the computations in a single cycle.