This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)

Industry-leading SAR and Delta-Sigma ADCs with easy-to-use design resources to enable premium performance

SAR ADC on tiny tapeout

Fully-differential asynchronous non-binary 12-bit SAR-ADC

A 10bit SAR ADC in Sky130

Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC

HSPICE and MATLAB simulation files of a tracking SAR ADC

12 bit SAR ADC IP in Skywater 130 nm PDK

Model SAR ADC with python!

This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online Internship 2020 by the ADC Team.

Digital Standard Cells based SAR ADC

12 bit SAR ADC for TinyTapeout 7

Simulink model for noise shaping SAR ADC

Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"

8 and 9 bit SAR ADC in IHP SG13G2

16-Bit SAR ADC, Single Supply, 4-20mA Acquisition System

No description available

No description available

The design process, a 4-bit SAR ADC and its different component was designed using Cadence Virtuoso software. This SAR ADC system consists of a bootstrapped sample-and-hold switch, a capacitive digital-to-analog converter (DAC), a dynamic comparator, and a SAR logic. Overall, the 4-bit SAR ADC designed and implemented in this project.

This is a SAR ADC Controller verilog implementation

No description available

An open source ADC using RAIL AMS open source framework.

IL2239 Project Course (SAR ADC Design)

Chipalooza Challenge SAR ADC 16 Bit

3 bit sar adc with real mixed signal simulation using xschem, ngspice, and verilator. Transistors used are from the open source sky130 PDK. Features a 3 bit DAC, fed into a sample and hold circuit, then fed into a comparator. The comparator creates a digital output value fed into the verilog block

No description available

No description available

HadCon2 is a credit-card sized general purpose I/O module for detector and experiment controls as well as for small data acquisition systems.It is the successor of the discontinued first version HadCon ( HADControl/HadShoPoMo general purpose board, HadCon @ Epics Wiki). The module has an ATMEL AT90CAN128 microcontroller providing a multitude of connectivity: I2C (8/4 fold (intern/extern) multiplexer), 6 channel 1-wire master, 8-channel 8bit DAC, galvanically isolated CAN - high-speed transceiver, 8-channel 10-bit SAR ADC, byte-oriented SPI, in total up-to 53 programmable I/O lines and optionally a Lattice MachX02 FPGA for fast data processing tasks. While the discontinued precursor HadCon had an SoC on-board, its successor HadCon2 has broken up this concept in favour of a more open access: It doesn't have any CPU on board, but a USB connector to directly allow communication with any type and size of computer (e.g. PC, raspberry PI, dreamplug, ...) having an USB port on one side and at the other end the microcontroller and the FGPA. This communication is based on an ASCII-based protocol in view of easy implementation in detector control systems like e.g. EPICS and LabVIEW.

Design 8 BIT SAR ADC , with 035 technology , with LTSpice simulation