This repository presents the mixed-signal design of an 8-bit SAR ADC using the SkyWater 130nm PDK, integrating a custom XSCHEM symbol for the Yosys-synthesized Spice output of Verilog-described SAR logic with the analog circuitry designed in XSCHEM. It serves as a demonstration of mixed-signal design flows utilizing iVerilog, Yosys, and XSCHEM.