🚀 preparing release v1.12.9

[readme] add link to nommu-linux port

fix(bus): SC.W returns 0 on success instead of stale memory data (#1520)

[changelog] add v1.12.8.10

[processor_check] refine LR/SC test

[package] update version ID

[rtl/rvs] minor edit

fix(bus): SC.W now returns 0 on success instead of stale memory data

[trng] add TRNG architecture configuration generics and ⚠️ rework control register layout (#1518)

[vivado_ip] add TRNG architecture configuration

[sw/example] update TRNG demo program

[changelog] add v1.12.8.9

[sim] add new TRNG generics to testbench

[trng] rework control register layout

[trng] radd TRNG architecture config generics