🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Ada-language framework

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

No description available

Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

Rust support for the open-source NEORV32 RISC-V microcontroller.

Formal verification (experiments) targeting the NEORV32 RISC-V processor.

Ada-based Hardware Abstraction Layer for the neorv32 SoC

NEORV32 integration test with LiteX

Playing around with the [`neorv32`](https://github.com/stnolting/neorv32) SoC on a [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start) Board with an Intel Cyclone IV E FPGA.

Custom hardware accelerator for image convolution operations (3x3 kernels)

🐍 Port of MicroPython for the NEORV32 RISC-V Processor.

RISC-V NEORV32 implementation for DE0-Nano, with SW examples (Fill in the build steps)

Cross-platform compatible firmware download tool for use with the NEORV32 bootloader, written in Python

Running DOOM on the NEORV32 CPU

A simple design showing the NeoRV32 executing code from an LSRAM in the FPGA to drive PWM and UART

XIP (eXecute In Place) Bootloader for the NEORV32 Processor

Master's thesis on FHE: integrating the Aloha-HE accelerator for CKKS into the NEORV32 RISC-V core

A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.

Core-NPU is an Open-source Wishbone NPU developed in VHDL to accelerate common ML operations by performing them in hardware

NEORV32 on ULX3S

RISC-V (NEORV32) on CYC1000

Notes and material on the NeoRV32 VHDL CPU

Support for writing Rust on NEORV32. (WIP)